`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Portland State University, Sprin 2014
// Engineer: Vijay E Arputharaj
// 
// Create Date:    19:56:12 04/18/2014 
// Design Name:    Top level module
// Module Name:    nexys3fpga 
// Project Name:  Rojobot world
// Target Devices: 
// Tool versions: 
// Description: Instantiates all design modules
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module Nexys3fpga (
	input 				clk100,          		// 100MHz clock from on-board oscillator
	input				btnl, btnr,				// pushbutton inputs - left and right
	input				btnu, btnd,				// pushbutton inputs - top and bottom
	input				btns,					// pushbutton inputs - center button
	input	[7:0]		sw,						// switch inputs
	
	output	[7:0]		led,  					// LED outputs	
	
	output 	[7:0]		seg,					// Seven segment display cathode pins
	output	[3:0]		an,						// Seven segment display anode pins	
	
//	output	[3:0]		JA,						// JA Header
	
	output	 Hsync,Vsync,						//Hsync & Vsync from DTG
	output [2:0] vgaRed,vgaGreen,				// VGA output from colorizer
	output [2:1] vgaBlue  						//
); 

	// internal variables
	wire 	[7:0]		db_sw;					// debounced switches
	wire 	[4:0]		db_btns;				// debounced buttons
	
	wire				sysclk;					// 100MHz clock from on-board oscillator	
	wire				sysreset;				// system  signal - asserted high to force reset
	
	wire 	[4:0]		dig3, dig2, 
						dig1, dig0;				// display digits
	wire 	[3:0]		dp;					// decimal points
				
	wire 	[31:0]		digits_out;	
				


	assign led=8'b1;
	// global assigns
	assign	sysclk = clkfb_in;
	assign 	sysreset = db_btns[0];
//	assign	JA = {sysclk, sysreset, 2'b0};

// internal variables for picoblaze and program ROM signals
// signal names taken from kcpsm6_design_template.v
	wire clk25;
	wire [10:0]	ICON_ROM_ADDR;
	wire [1:0]	ICON_ROM_DATA;
	wire [1:0] 		icon_out;	
	
	
// global assigns
assign kcpsm6_reset = sysreset;			// Picoblaze is reset w/ global reset signal
assign kcpsm6_sleep = 1'b0;				// kcpsm6 sleep mode is not used
				

		

		
wire [1:0] world_pixel,icon;					//Internal nets for video controller	
wire	[9:0]	pixel_row512, pixel_column512;  //Row and column pixel output from  DTG module
wire [9:0] pixel_row128, pixel_column128;		//Row and column pixel input to Bot & Icon modules
wire 		video_on;							// video enable signal from DTG
				
assign pixel_row128=pixel_row512>>2;			
assign pixel_column128=pixel_column512>>2;		//512x512 to 128x128 mapping

// instantiate the BOTSIM Picoblaze and its Program ROM




//instantiate the debounce module
	debounce 	DB (
		.clk(sysclk),	
		.pbtn_in({btnl,btnu,btnr,btnd,btns}),
		.switch_in(sw),
		.pbtn_db(db_btns),
		.swtch_db(db_sw)
	);	
		
	// instantiate the 7-segment, 4-digit display
	sevensegment SSB (
		// inputs for control signals
		.d0(dig0),
		.d1(dig1),
 		.d2(dig2),
		.d3(dig3),
		.dp(dp),
		// outputs to seven segment display
		.seg(seg),			
		.an(an),				
		// clock and reset signals (100 MHz clock, active high reset)
		.clk(sysclk),
		.reset(sysreset),
		// ouput for simulation only
		.digits_out(digits_out)
	);


	stage s1(
	// interface to the video logic
	.vid_row(pixel_row128),				// video logic row address
	.vid_col(pixel_column128),			// video logic column address

	.vid_pixel_out(world_pixel),		// pixel (location) value

	// interface to the system
	.clk (sysclk),						// system clock
	.reset(sysreset)				// system reset
	);



// instantiate the DCM module

dtg DTG1(
	.clock(clk25),					// 25M Hz clock input from DCM	
	.rst(sysreset),					// System reser
	.horiz_sync(Hsync),				//
	.vert_sync(Vsync), 				//Sync Outputs
	.video_on(video_on),			//Video enable signal
	.pixel_row(pixel_row512), 		//
	.pixel_column(pixel_column512)	// pixel location in 512x512 display
);




// insert this template into your top-level module to instantiate a DCM_SP and clock feedback buffer. 
// The DCM is configured to generate a divide-by-four clock output.

wire            clkfb_in,clk0_buf;
   
   // DCM clock feedback buffer
BUFG CLK0_BUFG_INST (.I(clk0_buf), .O(clkfb_in));


// DCM_SP: Digital Clock Manager Circuit
// Spartan-3E/3A, Spartan-6
// Xilinx HDL Libraries Guide, version 11.2

DCM_SP #(
.CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_inst (
.CLK0(clk0_buf), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(clk25), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clkfb_in), // DCM clock feedback
.CLKIN(clk100), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
// End of DCM_SP_inst instantiation

	//instantiate the colorizer module
	Colorizer C1(
   .vid_pixel_out(world_pixel),
   .icon(icon_out),
	.video_on(video_on),

	.red(vgaRed),
	.green(vgaGreen),
	.blue(vgaBlue)
	);

	//Instantiate ball icon module
	icon ball_icon(
	.pixel_row(pixel_row512),
	.pixel_column(pixel_column512),
	.LocX_reg(8'd64),			// X-coordinate of rojobot's location		
	.LocY_reg(8'd64),			// Y-coordinate of rojobot's location
	.BotInfo_reg(8'd0),
	.ROM_data(ICON_ROM_DATA),
	
	.ROM_addr(ICON_ROM_ADDR),
	.icon(icon_out)
   );
	
	//Instantiate icon ROM
	icon_rom ICON_ROM(
	.clka(clk25),
	.addra(ICON_ROM_ADDR),
	.douta(ICON_ROM_DATA)	
	);
	
	
endmodule